bi-cmos 8-bit parallel-input latched driver m 566 20 ap mitsubishi des cri pt i o n th e m 5 6620ap i s a semiconductor integrated circuit fabricated using bi-cmos technology. it contains bipolar 8 output drivers o f cmos latch. f e at ures l enable input for output control l low supply current .......................................i cc 10 m a at standby l input level is compatible with standard cmos l driver: withstand voltage .................................. .........bv ceo 3 50v large drive current .................................. (i o (max) =500ma) l wide operating temperature range ..................... ta=-20 ?+75 c app l i cat i o n thermal printer head dot driver, relay driver, solenoid driver f unct i o n when data is applied to inputs in1 ? in8 and latch input is set to ?? the data will be latchedance with the truth table. note that when an ?? signal is applied to the reset input, the latch will maintain the reset state. when the en input is set to ?? and the data maintained in the latch are ?? the corresponding output will be on and become ?? when both the latch and reset inputs are ?? the latch will maintain the prior state irrespective of input signals in1 ?in8. b l oc k d ia gr a m outline 22p4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? reset latch in1 in2 in3 in4 in5 in6 in7 in8 gnd reset input latch input parallel inputs en v cc o1 o2 o3 o4 o5 o6 o7 o8 com enable input parallel outputs common 22 19 20 21 1 4 3 2 18 5 17 6 16 7 15 8 14 9 13 10 12 11 m5 6620a p pi n c o n f i g urat i o n ( to p v i e w ) o1 o2 o3 o4 o5 o6 parallel outputs 20 21 19 18 17 16 15 14 13 12 22 1 2 3 4 5 6 7 8 9 10 11 o7 com o8 v cc in1 in2 in3 in4 in5 in6 in7 in8 gnd parallel inputs common en reset latch enable input reset input latch input (8 latch circuits)
bi-cmos 8-bit parallel-input latched driver m 566 20 ap mitsubishi t rut h t abl e l: low level h: high level x: low level or high level t-1: previous state t: current state h output: off state l output: on state input output on inn l h x x x latch h h x x l reset l l h x l en l l x h l t-1 x x x x l t h l h h l xl l l h h l o g i c di ag ram ( o n e c i r c u i t ) i n put / o u t p ut e q ui val e nt c i r cui t s 1 input circuits (inn, latch, reset) 2 input circuit (en) inn latch reset en v cc on (n = 1 ? 8) common block r in v cc gnd inn r in v cc gnd en ( n = 1 ?8)
bi-cmos 8-bit parallel-input latched driver m 566 20 ap mitsubishi 3 output circuits (o1 ? o8) symbol ratings unit parameter conditions abs o l ut e m axi m um rat i ng s (ta=-20 to 75 c, unless otherwise noted) v cc v i v o i o p d t opr t stg supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature output: off output: on ta=25 c -0.3 ? +8 -0.3 ? v cc +0.3 0 ?+50 500 1.25 -20 ? 75 -55 ? 125 v v v ma w c c limits min. typ. max. symbol conditions unit parameter rec o m m e nde d o perat i n g c o ndi t i o n (ta=-20 to 75 c, unless otherwise noted) v cc v o i o supply voltage output apply voltage output current (per circuit) output: off all outputs go in on state simultaneously. duty cycle < 15% 45 6 50 350 v v ma limits min. typ. max. symbol test conditions unit parameter el ect r i cal charact eri s t i cs (ta=25 c, v cc =5v, unless otherwise noted) high-level input voltage low-level input voltage input resistance low-level output voltage output leak current clamping diode forward voltage clamping diode reverse current supply current v ih v il r in v ol1 v ol2 v ol3 i olk v f i r i cc1 i cc2 ta=-20 ? 75 c v in =1.5 ? 3.5v i ol =100ma i ol =200ma i ol =350ma v o =50v i f =350v v r =50v en=5v, all other inputs = 0v en=0v, one output is on. 0.7v cc 0 50 1.0 v cc 0.3v cc 2000 1.1 1.3 1.6 50 2 50 10 1.5 v v k w v v v m a v m a m a ma gnd v cc com on
bi-cmos 8-bit parallel-input latched driver m 566 20 ap mitsubishi t i m i ng chart limits min. typ. max. symbol test conditions unit parameter sw i t chi ng chara ct e r i s t i cs (ta=25 c, v cc =5v, unless otherwise noted) t plh t phl t plh t phl t plh low-to-high-level output propagation time from input latch to output on high-to-low-level output propagation time from input latch to output on low-to-high-level output propagation time from input en to output on high-to-low-level output propagation time from input en to output on low-to-high-level output propagation time from input reset to output on v ih =5v v il =0v r l =100 w c l =15pf 5 0.5 5 0.5 5 m s m s m s m s m s t i m i ng chart limits min. typ. max. symbol test conditions unit parameter t i m i ng req u i r e m e n t s (ta=-20 to 75 c, unless otherwise noted) t w(l) t w(r) t su t h latch pulse width reset pulse width data setup time data hold time 0.1 0.1 0.05 0.1 m s m s m s m s t plh 2.5v en on reset latch 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v t phl t plh t phl t plh inn enable input output reset input latch input parallel input 50% t w(l) t su inn latch reset 50% t h 50% 50% t w(r) 50% 50% reset input latch input parallel input v cc 0v
bi-cmos 8-bit parallel-input latched driver m 566 20 ap mitsubishi t est ci rcui t t ypi cal charact eri s t i cs v cc r l c l input pg 50 w m5 6620a p output the in put waveform: t r 20ns, t f 20ns the capacitance c l includes the wiring stray capacitance and probe input capacitance. thermal derating (absolute maximum rating) ambient temperature t a ( c ) 0 0 power dissipation p d(max) (w) 0.5 1.0 1.5 25 50 75 100 t a = -20 c t a = 25 c t a = 75 c supply voltage vs. supply current (one circuit : on) supply voltage v cc (v) 0 0 supply current i cc (ma) 123 45 67 89 1 0 1 2 3 4 5 20 18 16 14 12 10 8 6 4 2 0 01 2 in tput current i i ( m a) input voltage v i (v) t a = 75 c t a = 25 c t a = -20 c t a = -20 c t a = 25 c t a = 75 c 34 5 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 0 1234 5 input voltage vs. input current (inn, latch and reset) input voltage vs. input current (en) in put current i i ( m a) input voltage v i (v)
bi-cmos 8-bit parallel-input latched driver m 566 20 ap mitsubishi duty cycle vs. allowable output current duty cycle (%) 0 0 output current i o (ma) 40 60 80 100 100 200 300 400 500 20 low-level output voltage (v) 0 0 low-level output current (ma) 0.5 1 1.5 2 100 20 0 30 0 40 0 50 0 60 0 70 0 low-level output voltage vs. current duty cycle vs. allowable output current duty cycle (%) 0 0 output current i o (ma) 40 60 80 100 100 200 300 400 500 20 t a = 75 c t a = 25 c t a = -25 c , t a = 25 c repetitive frequency > 10h z each figure in a circle shows the number of output circuits which operate simultaneously. current value : output current per circuit 1 2 3 4 5 6 7 8 t a = 75 c repetitive frequency > 10h z each figure in a circle shows the number of output circuits which operate simultaneously. current value : output current per circuit 1 2 3 4 5 6 7 8
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